The present invention relates to a two-dimensional focal plane array and a driving method therefor.
A conventional focal plane array is explained referring to the drawings. FIG. 10 is a block diagram showing the structure of. A conventional image sensor of CSD (charge sweep device) system shown in IEEE Journal of Solid State Circuits, Vol. SC-22, p.1124 to 1129 (hereinafter referred to as "report 1"), which is an example of a conventional focal plane array. In FIG. 10, numerals 111 to 118, 211 to 218 and 311 to 318 denote photodetectors; numerals 121 to 128, 221 to 228 and 321 to 328 denote the transfer gates for controlling the transfer of signal charges stored or accumulated in the photodetectors 111 to 118, 221 to 218 and 311 to 318 to vertical charge transfer devices 130, 230 and 330; numerals 140, 240 and 340 denote the storage gates for storing temporarily the signal charges transferred through the vertical charge transfer devices 130, 230 and 330; numerals 150, 250 and 350 denote the storage control gates for controlling the transfer of the signal charges stored on the storage gates 140, 240, and 340 to horizontal charge transfer devices 500; numeral 600 denotes a preamplifier for generating the voltage signal according to the signal charge amount outputted from the horizontal charge transfer device 500; numeral 700 shows an output section of the image sensor; numeral 800 shows a pixel row selection circuit; and numeral 900 shows a drive circuit for the vertical charge transfer devices 130, 230 and 330. The photodetector comprises a photodiode or a Schottky barrier diode; the transfer gate comprises MOS transistors; the vertical charge transfer device comprises CSD; the storage gate comprises MOS capacitors; and the horizontal charge transfer device comprises a CCD (charge coupled device); and storage control gate comprises MOS transistors (a source electrode and a drain electrode are constituted respectively of storage gates and horizontal charge transfer devices).
FIG. 11 is a block diagram showing a pixel row selection circuit and a transfer gate of the image sensor shown in FIG. 10. The pixel row selection circuit 800 comprises shift registers. Numerals 801 to 808 denote each stage of the pixel row selection circuits. Each stage of the pixel row selection circuit 800 is connected respectively to three transfer gates provided along the horizontal direction. For example, the first stage 801 of the pixel row selection circuit is connected to the transfer gates 121, 221 and 321, and the second stage 802 of the pixel row selection circuit is connected to the transfer gates 122, 222 and 322.
FIG. 12 is a block diagram showing the drive circuit for the image sensor and the vertical charge transfer device as shown in FIG. 10. Each of the vertical charge transfer devices 130, 230 and 330 comprises CSD. In FIG. 12, numerals 131 to 138 denote the respective gate electrodes (hereinafter, to be simply referred to as "vertical gate electrode") in the vertical charge transfer device 130; the numerals 231 to 238 denote the respective gate electrodes (hereinafter, to be simply referred to as "vertical gate electrode") of the vertical charge transfer device 230; numerals 331 to 338 denote the gate electrodes of the vertical charge transfer device 330. Further, the drive circuit 900 comprises a MOS switch circuit or a shift register circuit. The numerals 901 to 908 denote the respective gate electrodes (hereinafter, to be simply referred to as "drive gate electrode") of the drive circuits. Each of the drive gate electrodes 901 to 908 is connected to the three vertical gate electrodes provided along the horizontal direction For example, the drive gate electrode 901 is connected to the vertical gate electrodes 131, 231 and 331, and the drive gate electrode 902 is connected to the vertical electrodes 132, 232 and 332. Accordingly, the respective drive gate electrodes give clock signals respectively to three vertical gate electrodes provided along the horizontal direction. In the conventional image sensor described above, for simple explanation, there are shown 3 photodetectors in the horizontal direction and 8 in the vertical direction, respectively, but normally in practice there are several hundreds of the photodetectors provided both in horizontal and vertical directions. As the number of the photodetectors is equal to the number of pixels in the image sensor, the conventional image sensors have in practice several hundred pixels in horizontal and vertical directions, respectively.
Referring to FIGS. 10 to 12, the transfer gates 121 to 128, 221 to 228, and 321 to 328 and the vertical gate electrodes 131 to 138, 231 to 238, and 331 to 338 are shown as discrete structures not to be integrated with each other. However, as shown in the foregoing report 1, the vertical gate electrode and the gate electrode of the transfer gate adjacent to vertical gate electrode (hereinafter to be referred to simply as "trans gate electrode") may be formed in a single gate electrode. By controlling independently the impurity concentrations in the lower channels in the vertical gate electrode and the trans gate electrode, the transfer gate and the vertical charge transfer device can be operated independently.
The operation of the image sensor is explained by referring to FIG. 13. FIG. 13 is a timing chart showing the clock signal to be outputted by the pixel row selection circuit in the conventional image sensor as shown in FIG. 10. In FIG. 13, symbols .phi.801 to .phi.808 show the outputs of the respective stages in the pixel row selection circuit. The period from a time when the output of the n-th stage of the pixel row selection circuit reaches the high (H) level to another time when the output of the (n+1)-th stage of the pixel row selection circuit reaches the high (H) level (hereinafter referred to as "H level") is one horizontal period, i.e., the time while the image sensor scans one horizontal line (in the drawing, shown by "tH"). The transfer gate transfers the signal charge in the photodetector to the vertical charge transfer device when a clock signal is generated in the stage of the pixel row selection circuit to which the transfer gate is connected. Accordingly, by generating a clock signal in any stage in the pixel row selection circuit in every horizontal period, the image sensor can be operated so that the signal charge in one horizontal line is transferred to the vertical charge transfer device in every horizontal period. The above horizontal line comprises a plurality of optical detectors adjacent to each other in the horizontal direction among the two-dimensionally arrayed optical detectors. In FIG. 10, for example, the optical detectors 111, 211 and 311 are the plural optical detectors adjacent to each other in the horizontal direction.
Referring to FIGS. 14 and 15, a detailed description is given on the signal charges which are to be transferred to the horizontal gate electrode.
FIGS. 14 (a) and 14(b) are illustrations showing the structure on the section of A--A line in FIG. 10 and the potential on the section of A--A line. FIG. 14(a) is an illustration of the sections of the vertical gate electrodes 131 to 138, storage gate 140, storage control gate 150, gate electrode 501 to which the above storage control gate 150 is connected from the horizontal charge transfer device 500 (hereinafter to be referred to as "horizontal gate electrode"), and a substrate 10 on which the constitution elements of the image sensor are to be formed (not illustrated in FIG. 10). Further, though not illustrated, there are insulating films provided between the vertical gate electrodes 131 to 138, storage gate 140 and storage control gate 150, and horizontal gate electrode 501 and the substrate 10. FIG. 14(b) is an illustration showing the potential in the lower part of the vertical gate electrodes 131 to 138, storage gate 140, storage control gate 150 and horizontal gate electrode 501 shown in FIG. 14(a). To the vertical gate electrodes 131 to 138, the signals .phi.901 to .phi.908 from the drive gate electrode are inputted, respectively. In FIGS. 14(a) and 14(b) there is shown a condition after applying a clock signal to the transfer gate from the pixel row selection circuit and transferring (reading out) the signal charge to the vertical charge transfer device from the photodetector. In FIG. 14, the parts shown by QS1 and QS2 are the signal charges from one photodetector. As shown in FIGS. 14(a) and 14(b), the signal charges QS1 and QS2 are transferred to the lower part of the horizontal gate electrode 501 in the interval between the timings T1 to T7.
FIG. 15 is a timing chart showing an output of the drive gate electrode which is connected to the vertical gate electrode shown in FIG. 14(a). In FIGS. 14(a) to 14(b) and 15, timings T1 to T5 show the horizontal scanning periods, and timings T6 and T7 show the horizontal retrace periods. The horizontal period comprises one horizontal retrace period and one horizontal scanning period. In FIG. 15, symbols .phi.901 to .phi.908 show the electrical signals to be applied respectively to the vertical gate electrodes 131 to 138 from the drive gate electrode, and symbols .phi.ST and .phi.SC show the electrical signals to be applied respectively to the storage gate 140 and the storage control gate 150 shown in FIG. 14(a). Though not illustrated, an electrical signal to be applied to the horizontal gate electrode 501 is shown by .phi.H.
First, in the timing T1, because the signals .phi.901 and .phi.902 show H levels, the signal charge QS1 is stored on the lower parts of the vertical gate electrodes 131 and 132. In the timings T1 to T2, the signal .phi.901 changes to a low (L) level (hereinafter referred to as "L level"), and the signal .phi.902 changes to L level after the signal .phi.901. Simultaneously, at the time when the signal .phi.901 changes to L level, the signal .phi.903 changes to H level; at the time when the signal .phi.902 changes to L level, the signal .phi.904 changes to H level. Accordingly, in the timing T2, the signal charge QS1 is stored on the lower part of the vertical gate electrodes 133 and 134. In FIG. 14(b), the state of the signal charge QS1 shifting from the lower part of the vertical gate electrodes 131 and 132 to the lower part of the vertical gate electrodes 133 and 134 is shown by an arrow B1.
In the timings T2 to T3, the signal .phi.903 changes to L level, and the signal .phi.904 changes to L level after the signal .phi.903. Simultaneously, at the time when the signal .phi.903 changes to L level, the signal .phi.905 changes to H level; at the time when the signal .phi.904 changes to L level, the signal .phi.906 changes to H level. Accordingly, in the timing T3, the signal charge QS1 is stored in the lower part of the vertical gate electrodes 135 and 136. In FIG. 14(b), the state of the signal charge QS1 shifting from the lower part of the vertical gate electrodes 133 and 134 to the lower part of the vertical gate electrodes 135 and 136 is shown by an arrow B4.
In the timings T3 to T4, the signal .phi.905 changes to L level, and the signal .phi.906 changes to L level after the signal .phi.905. Simultaneously, at the time when the signal .phi.905 changes to L level, the signal .phi.907 changes to H level; at the time when the signal .phi.906 changes to L level, the signal .phi.908 changes to H level. Also, in the timings T3 to T4, the signal .phi.ST always indicates H level, and the signal .phi.SC always indicates L level. Accordingly, in the timing T4, the signal charge QS1 is stored in the lower part of the vertical gate electrodes 137 and 138 and the storage gate 140. In FIG. 14(b), the state of the signal charge QS1 shifting from the lower part of the vertical gate electrodes 135 and 136 to the lower part of the vertical gate electrodes 137 and 138 and the storage gate 140 is shown by an arrow B5 and an arrow B6.
In the timings T4 to T5, the signal .phi.907 changes to L level, and the signal .phi.908 changes to L level after the signal .phi.907. Also, in the timings T4 to T5, the signal .phi.ST always indicates H level, and the signal .phi.SC always indicates L level. Accordingly, in the timing T5, the signal charge QS1 is stored on the lower part of the storage gate 140.
On the other hand, in the timing T1, because the signals .phi.905 and .phi.906 indicate H level, the signal charge QS2 is stored in the lower parts of the vertical gate electrodes 135 and 136. Between the timing T1 and the timing T2, the signal .phi.905 changes to L level, and the signal .phi.906 changes to L level later than the signal .phi.905. Simultaneously, at the time when the signal .phi.905 changes to L level, the signal .phi.907 changes to H level, and at the time when the signal .phi.906 changes to L level, the signal .phi.908 changes to H level. Also, in the timings T1 to T2, the signal .phi.ST always indicates H level, and the signal .phi.SC always indicates L level. Accordingly, in the timing T2, the signal charge QS2 is stored in the lower part of the vertical gate electrodes 137 and 138 and the storage gate 140. In FIG. 14(b), the state of the signal charge QS2 shifting from the lower part of the vertical gate electrodes 135 and 136 to the lower part of the vertical gate electrodes 137 and 138 and the storage gate 140 is shown by an arrow B2 and an arrow B3.
In the timings T2 to T3, the signal .phi.907 changes to L level, and the signal .phi.908 changes to L level after the signal .phi.907. Also, in the timings T2 to T3, the signal .phi.ST always indicates H level, and the signal .phi.SC always indicates L level. Accordingly, in the timing T3, the signal charge QS2 is stored on the lower part of the storage gate 140.
As shown in FIG. 14, in the timing T5, the signal charges QS1, QS2 are stored in the lower part of the storage gate 140. In the timings T5 to T7, when the signals .phi.SC and .phi.H change to H levels, and the signal .phi.ST changes to L level after the signals .phi.SC and .phi.H change to H levels, the signal charges QS1 and QS2 are stored on the lower part of the horizontal gate electrode 501.
In the timings T1 to T7, the signal charges QS1, QS2 stored in the lower part of the storage gate 140 in the horizontal scanning period comprising the timings T1 to T5 are outputted from the image sensor through the horizontal charge transfer device 500 and preamplifier 600 in the next horizontal period after the previous horizontal period which includes the timings T1 to T7 shown in FIG. 14. In the horizontal scanning period including the timings T1 to T5, the signal charges are stored in the lower part of the storage gates 240, 340 (ref. FIG. 10), respectively, in the same manner as in the signal charge QS1 and QS2. The signal charges stored in the lower part of the storage gates 140, 240 and 340 are sequentially outputted from the image sensor through the horizontal charge transfer device 500 and the preamplifier 600.
In the timings T1 to T5, the potential on the lower part of the horizontal gate electrode 501 may be between H level and L level shown by symbols C1 to C5.
There is given a detailed explanation on the operation of the pixel row selection circuit 800 shown in FIG. 10. FIG. 16 is a timing chart showing the clock signals to be outputted from the pixel row selection circuit shown in FIG. 10. The pixel row selection circuit can be constituted in general by a shift register for operating by inputting the electrical signals .phi.T1 and .phi.T2 as a two-phase clock signal. .phi.TS shows an electrical signal which includes a starting clock signal to determine the start of operation of the pixel row selection circuit. The outputs .phi.801 to .phi.808 of the pixel row selection circuit are synchronized with the signal .phi.T1, which is outputted one by one in the order of the outputs .phi.801 to .phi.808 on each horizontal period tH according to the start clock signal of the signal .phi.TS.
It is also possible to design the pixel row selection circuit so as to operate the pixel row selection by using an interlace scanning system which is a standard television scanning system, for example, RS170. Also, there is disclosed in Japanese Unexamined Patent Publication No. 292405/1993 a system which changes over the interlace operation system externally only by an electrical signal, wherein there is disclosed a technique which permits the selection of the optimum interlace system according to the condition by using the focal plane array. In such a method, changeover can be made between the field storage system for reading out the signal charge of the photodetector of all pixels arranged in the focal plane array in each field, and the frame storage system for reading out only once in one frame the signal charge of the photodetector of each pixel.
According to the conventional CSD system, that is, focal plane array as stated above, changeover can be performed between the field storage system and the frame storage system. However, the circuits necessary for realizing the above-mentioned change are complicated, and the number of the electric signals to be inputted to the focal plane array also increases. Additionally, there are such problems as not to be possible to apply optional interlace or multifarious scanning methods such as scanning a part of the pixels.
Though it is possible to design a pixel row selection circuit so as to permit random access, such system involves problems that while the diversified uses are increased beyond necessity, the clock signal inputs from external source increase to make the control complicated.
The present invention solves the above-mentioned problem and provides, a CSD system focal plane array having a simple structure in which a pixel row selection circuit is mounted wherein simple and multifarious scanning can be made by only inputting a small number of clock signals.